The present invention relates to an ATM switch for switching and processing packets having a fixed length, called ATM cells (to be hereinafter referred to as cells), and more particularly to a packet switch for carrying out a switching process on the basis of a routing tag, called a header, given to each packet having a fixed length.
An ATM switch is well known as an example of a packet switching apparatus. In order to effectively utilize memory regions for storing the cells, in general, a common buffer memory for storing the cells to each output port is provided in the ATM switch so that the cells stored in the buffer memory may be switched and processed. Such an ATM switch is also called a common buffer type switch because it stores the cells to the different output ports and switches the cells stored in the common cell buffer memory.
The conventional ATM switch is composed of a multiplexer for multiplexing cells input from each external input port, a cell buffer memory for storing the cells multiplexed by the multiplexer, a demultiplexer for multiplexing and outputting the cells stored in the cell buffer memory and for demultiplexing the cells thus multiplexed, and an address controller for controlling addresses indicative of the memory regions of the cells stored in the cell buffer memory.
The address controller is composed of address registers each provided for associated output ports for storing addresses indicative of the memory regions for writing the cells to be stored next in the cell buffer memory, a write controller for controlling each write address register, readout address registers each provided for associated output ports for storing the readout address of the cells to be output to the demultiplexer next, a readout controller for controlling each readout address register, a controller for controlling the write controller and the readout controller, and a vacant address buffer memory for storing vacant addresses.
The common buffer type switching apparatus is, in general, composed of a common buffer using a logic FIFO (First In First Out) for every output port. The common buffer of the common buffer type switching apparatus is so constructed that the addresses indicative of the memory regions storing the cells to respective output ports are connected in relation in a chain-like manner by pointers. The operation of the address controller using this structure will be described. The address of the cell, to be output next, connected by the address pointer chain for each output port is indicated by each readout address. Namely, the cell stored in the memory region designated by the address pointed out by the readout address is the oldest cell in the cells to the corresponding output port and is the cell to be output next.
When the cell stored in the address indicated by the readout address is output, subsequently, a level of the address pointer corresponding to the address is read out, the level of the address pointer is input into the readout address, and this is the address to be read out next.
Also, the header of the cell which has been newly input is analyzed by the address controller, and is stored in the memory region corresponding to the address indicated by the write address pointer corresponding to the output port. Thereafter, a vacant address is read out from the vacant address memory to become a next write address and is stored in the cell buffer memory and the write address. Thus, the logic FIFO corresponding to each output port is formed. With such an arrangement, it is necessary to effect a control for the chain-like connection by using the address pointer for each output port, and to further effect a control by providing the output address to be read out next for each output port and the write address to be written next for each output port in the form of a pair. In addition, it is necessary to provide the vacant address controller for controlling the vacant addresses in a batch manner. In view of these requirements, an overall control system is needed for these controls together.
Also, the ATM switch requires a "multi-port function". The multi-port function means a function of outputting the cell, input from an input port, to a plurality of ports. In order to realize the multi-port function in the above-described ATM switch, a method is provided in which the cell input from the input port is copied into a plurality of copies when input and is stored in the cell buffer memory. The method however suffers from a problem that a writing speed to the cell buffer memory would be N times larger than the case where the multi-port function is not provided. Also, a method is used in the conventional ATM switch, in which the addresses indicative of the memory regions which store the cells are connected in the chain-like manner by the address pointers. It is therefore impossible to branch the address pointers for transmitting the same cell to the different output ports. Thus, it would be difficult to realize the multi-port function. Also, there is another feasible method in which the input cell is repeatedly read out to the output ports when the input cell is output to the output port. In this method, the number of the readouts of the cell stored in the cell buffer memory is calculated and the cell is canceled when the cell has been output to all the copy output ports. Accordingly, in order to count the number of the readouts, a counting means is additionally needed.
Also, in the ATM switch, it is important to know how many cells stay in the cell buffer memory. For example, in a telecommunication as for audio data in which a change of a delay time would largely affect the transmission quality, it is necessary to suppress the change of the transmission delay. The conventional apparatus for canceling the cells which suffers from remarkable delay change is composed of a counter for generating a clock, a time stamp adder for adding the clock generated by the counter from each input port to the input cell, a cell switch for switching the cells output from the time stamp adder, and a cell output controller provided for each output port for calculating a difference between the time stamp information added to the cell output from the cell switch and a current time transferred from the counter and for controlling the output of the cell in response to the result of the calculation. The clock time produced by the counter is added to the cell input into this apparatus by each time stamp adder provided for each input port and is transferred to the cell switch. In the cell switch, the switching operation is carried out on the basis of the routing information added to the cell, and the result is transferred to each cell output controller provided for each output port. Each cell output controller seeks a difference between the time stamp information added to the cell and the current time produced by the counter. Each cell output controller nullifies the cell since the delay exceeds the upper limit in the case where the difference is larger than a predetermined level. Thus, it is possible to nullify the cell which suffers from a large delay. However, since the cell having the large delay generated by the ATM switch is nullified until it is transferred to the cell output controller, the cell to be nullified occupies the memory regions within the cell buffer memory of the ATM switch. Thus, disadvantageously, it is impossible to effectively utilize the memory regions for storing the cell.
As described above, there are cases that the cell transfer delay would be produced in the ATM switch. The ATM switch having a priority function for output the cell with a priority out of the accumulated cells has been conventionally proposed. In the proposed ATM switch, the priority information is added to each cell stored in the cell buffer memory of the ATM switch, and the readout of the cell is controlled on the basis of the priority information. However, it is necessary to search the cell to be output with priority while depending upon the address pointer for every output port. Thus, the conventional system suffers from a problem that the further complicated control is required, in addition to the above-described control operation.